1. Field of the Invention
The present invention relates to a method for controlling a voltage of a DC link for an electric vehicle, and more particularly to a method for controlling a voltage of a DC link for an electric vehicle, which can reduce a capacitance of the DC link interposed between an inverter and a DC/DC converter.
2. Description of the Related Art
A vehicle using a battery as a power source like an electric vehicle or a hybrid vehicle has a DC/DC converter for raising the battery voltage and an inverter for driving a motor. The DC/DC converter and the inverter have a DC link interposed therebetween, and the DC link has a mass storage capacitor for buffering a voltage and a current. Generally, the DC link employs a great mass storage capacitor for reducing a voltage fluctuation ratio between the DC/DC converter and the inverter. In other words, the DC link employs an electrolytic capacitor, or a film capacitor having large volume.
However, since such a capacitor of the DC link has a large-size and an inferior thermal characteristic, an electrolytic solution contained in the capacitor may be leaked from the capacitor in the form of gas or liquid when the capacitor is used for a long time or if heat is applied to the capacitor, thereby shortening the life span of the capacitor. In addition, since the inner space of a vehicle is extremely restricted, an effort to reduce the number of replaced capacitors or attached capacitors is being made.
FIG. 1 schematically illustrates the conventional power system of the electric vehicle or the hybrid vehicle.
As shown in FIG. 1, conventionally, a power system of a vehicle employing electricity as a power source includes a battery 1, a DC/DC converter 4, a DC link 5, an inverter 6, a motor 7, and a control part 80.
The battery 1 is an energy source having a predetermined potential difference, the DC/DC converter 4 raises the voltage of the battery 1 to a predetermined voltage, the DC link 5 flattens the voltage raised by the DC/DC converter 4, the inverter 6 outputs an AC voltage having a predetermined voltage and a predetermined frequency to the motor 7, and the motor 7 rotates with a predetermined rotational frequency and a predetermined torque. In addition, the control part 80 controls the DC/DC converter 4 and the inverter 6 through a pulse width modulation scheme by performing feedback with respect to a current outputted from the inverter 6 and a voltage of the DC link 5. In FIG. 1, reference numerals 81 and 81′ represent converters for converting a 3-phase current coordinate inputted to the motor 7 or the inverter 6 into a 2-phase current coordinate, and reference numerals 83 and 85 represent PWM generators, reference numeral 82 represents an inverter controller, and reference numeral 84 represents a converter controller.
In addition, although the DC/DC converter 4 may have various types, the present invention employs a Buck-Boost converter having a coil 2 and two switches as an example. The inverter 6 may include six switches. Herein, it is natural that the DC link 5 connecting the DC/DC converter 4 to the inverter 6 has at least one mass storage capacitor 5a installed on the DC link 5.
FIG. 2 illustrates only the capacitor 5a of the DC link 5.
In FIG. 2, currents icon, icap, and iinv represent a current flown from the DC/DC converter 4, a current flowing toward the capacitor 5a of the DC link 5, and a current flowing toward the inverter 6, respectively. In FIG. 1, if the current icon from the DC/DC converter 4 is equal to the current iinv toward the inverter 6, the current icap toward the capacitor 5a of the DC link 5 becomes zero (0) through Kirchhoff's law. That is, if icon=iinv, icap=0. In other words, if icap=0, a voltage VDC of the DC link 5 is constantly maintained. Accordingly, if the current icon of the DC/DC converter 4 follows the current iinv when the motor 7 is accelerated, decelerated, or stopped, the capacity of the capacitor 5a in the DC link 5 may be minimized.
FIG. 3 is a block diagram for explaining the conventional method for controlling a voltage of a typical DC link. Herein, the control block diagram is obtained through modeling operations performed by hardware or software within and around the control controller 84 using all kinds of equations.
An inner loop IL_1 in the block diagram is a control loop for the current icon of the DC/DC converter 4 as generally known and includes a proportional-integral controller 10. In addition, an outer loop (OL) is a control loop for a voltage Vdc of the DC link 5 and includes a proportional-integral controller 8. In addition, another inner loop IL_2 is a control loop for the current iinv of the inverter 6 and includes a compensator 14. A low pass filter 12 may be installed and used in the compensator 14 for compensating the current iinv of the inverter 6. In FIG. 3, “L” and “C” included in the converter 86 represent the coil 2 used in the DC/DC converter 4 and the capacitor 5a of the DC link 5, respectively.
Reference numeral 9 represents a current node receiving a capacitor current reference i*cap and the capacitor current icap. Reference numeral 11 represents a voltage node receiving a battery voltage VB together with a voltage converted from a current through the proportional-integral controller 10.
FIG. 4 is a graph illustrating a relationship between time and the pulse inverter current.
As shown in FIG. 3, the low pass filter 12 is used in the compensator 14 in order to compensate the inverter current iinv. In other words, an average 16 of the inverter current shown in FIG. 4 is obtained using the low pass filter 12 and applied to the current node 9 receiving the capacitor current reference i*cap. Then, the applied compensation term is delivered to the converter 86 through the proportional-integral controller 10, so that the inverter current iinv is compensated. Accordingly, the voltage VDC of the DC link is constantly maintained.
Herein, the block diagram for controlling the voltage of the typical DC link shown in FIG. 3 will be described. The compensator 14 is used for compensating the inverter current iinv, includes the low pass filter 12, and supplies the average 16 of the inverter current to the current node 9. It is natural that the compensation term supplied to the current node 9 is delivered to the converter 86 through the proportional-integral controller 10 in order to compensate the inverter current.
However, this proportional-integral controller 10 inevitably causes a phase delay due to a time delay of a signal. In addition, the low pass filter 12 used for finding the average 16 of the inverter current inevitably causes a phase delay due to a time delay of a signal.
Accordingly, it is difficult to compensate the instantly changed inverter current iinv. In other words, the current icon of the DC/DC converter 4 does not fully follow the current iinv of the inverter 6 due to phase delays caused by the low pass filter 12 and the proportional-integral controller 10, respectively.
In addition, the mass storage capacitor 5a of the DC link 5 must be used due to the disadvantages described above such that the voltage fluctuation ratio is reduced. Accordingly, capacitor installation costs increase, and a wide capacitor installation space is required.